1. Field of the Invention
The present invention relates to the field of microprocessors; more particularly, the present invention relates to a method and apparatus for computing a sum of absolute differences.
2. Description of Related Art
A sum of absolute differences is used in many applications including video applications such as Motion Pictures Expert Group (MPEG) encoding.
One method of computing a packed sum of absolute differences (PSAD) of packed data A having eight byte elements A.sub.0 . . . A.sub.7 and packed data B having eight byte elements B.sub.0 . . . B.sub.7 is to compute Ai-Bi and Bi-Ai for each value of i from 0 to 7, select the results that are non-negative, and add the non-negative results together. One implementation uses sixteen adders (two adders for each pair of byte elements), eight muxes (to select the non-negative values from each pair of results) and an adder tree to sum the non-negative results.
As more devices are used, more silicon area is needed in a semiconductor device. Semiconductor devices generally have a cost proportional to the silicon area used. Therefore, it is desirable to reduce the number of devices used to perform the PSAD instruction.
One method of computing a PSAD with less devices is to use the same device to serially operate on multiple data elements. For example, one adder may compute A.sub.0 -B.sub.0 and B.sub.0 -A.sub.0 sequentially, another may compute A.sub.1 -B.sub.1 and B.sub.1 -A.sub.1 sequentially, etc. This reduces the number of adders (silicon area) used, but increases the amount of time required to compute a PSAD.
What is needed is a method and apparatus to reduce the amount of silicon area required to implement a PSAD instruction without increasing the time required to compute the PSAD.